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提交从正点原子mini板的程序移植过来的工程
2024-11-30 10:27:03 +08:00
:020000040800F2
根据安富莱的usart底层，缝合了ir controller的RXNE接收中断来接收数据的逻辑。
2025-05-08 23:18:49 +08:00
:10000000E80C0020050100080D0100080F010008A0
1. 提交完成debuglog的程序，利用printf重定向，用usart2作为打印调试日志的串口；2. 上传数据手册。
2025-05-05 22:37:13 +08:00
:10001000110100081301000815010008000000008C
:1000200000000000000000000000000017010008B0
根据安富莱的usart底层，缝合了ir controller的RXNE接收中断来接收数据的逻辑。
2025-05-08 23:18:49 +08:00
:1000300019010008000000001B010008510500081C
1. 提交完成debuglog的程序，利用printf重定向，用usart2作为打印调试日志的串口；2. 上传数据手册。
2025-05-05 22:37:13 +08:00
:100040001F0100081F0100081F0100081F01000810
:100050001F0100081F0100081F0100081F01000800
:100060001F0100081F0100081F0100081F010008F0
:100070001F0100081F0100081F0100081F010008E0
:100080001F0100081F0100081F0100081F010008D0
:100090001F0100081F0100081F0100081F010008C0
:1000A0001F0100081F0100081F0100081F010008B0
根据安富莱的usart底层，缝合了ir controller的RXNE接收中断来接收数据的逻辑。
2025-05-08 23:18:49 +08:00
:1000B000FD050008010600081F0100081F010008D7
1. 提交完成debuglog的程序，利用printf重定向，用usart2作为打印调试日志的串口；2. 上传数据手册。
2025-05-05 22:37:13 +08:00
:1000C0001F0100081F0100081F0100081F01000890
根据安富莱的usart底层，缝合了ir controller的RXNE接收中断来接收数据的逻辑。
2025-05-08 23:18:49 +08:00
:1000D0001F0100088D080008C90800081F0100085A
1. 提交完成debuglog的程序，利用printf重定向，用usart2作为打印调试日志的串口；2. 上传数据手册。
2025-05-05 22:37:13 +08:00
:1000E0001F0100081F0100081F010008DFF810D0E1
根据安富莱的usart底层，缝合了ir controller的RXNE接收中断来接收数据的逻辑。
2025-05-08 23:18:49 +08:00
:1000F00000F02CF80048004705160008AFF3008018
:10010000E80C00200648804706480047FEE7FEE767
1. 提交完成debuglog的程序，利用printf重定向，用usart2作为打印调试日志的串口；2. 上传数据手册。
2025-05-05 22:37:13 +08:00
:10011000FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE7B7
根据安富莱的usart底层，缝合了ir controller的RXNE接收中断来接收数据的逻辑。
2025-05-08 23:18:49 +08:00
:100120009D050008ED00000840EA01039B0703D08D
1. 提交完成debuglog的程序，利用printf重定向，用usart2作为打印调试日志的串口；2. 上传数据手册。
2025-05-05 22:37:13 +08:00
:1001300009E008C9121F08C0042AFAD203E011F826
:10014000013B00F8013B521EF9D27047064C074DA7
:1001500006E0E06840F0010394E807009847103497
根据安富莱的usart底层，缝合了ir controller的RXNE接收中断来接收数据的逻辑。
2025-05-08 23:18:49 +08:00
:10016000AC42F6D3FFF7C6FF541800087418000815
1. 提交完成debuglog的程序，利用printf重定向，用usart2作为打印调试日志的串口；2. 上传数据手册。
2025-05-05 22:37:13 +08:00
:100170002DE9F0410246002500260020002300243E
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:1002600091F803C0BCF1480F07D100F1080C4FF022
:10027000010808FA0CF8C2F81080401C0828CED3F8
完成了初版的app_motor程序，但是PA2的PWM万用表量还是3.3V，本地模拟器的逻辑分析仪是可以看到波形的，明天拿逻辑分析仪量一下到底是什么样的波形
2025-05-06 22:53:45 +08:00
:100280005460BDE8F0814161704701617047000032
根据安富莱的usart底层，缝合了ir controller的RXNE接收中断来接收数据的逻辑。
2025-05-08 23:18:49 +08:00
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提交从正点原子mini板的程序移植过来的工程
2024-11-30 10:27:03 +08:00
:04000005080000ED02
:00000001FF
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